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言語種別	英語
発行・発表の年月	2013/01
形態種別	学術論文
査読	査読あり
標題	Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver　With Low-Power Analog and Digital Baseband Circuitry
執筆形態	共著
掲載誌名	IEEE Journal of Solid-State Circuits
掲載区分	国外
出版社・発行元	IEEE
巻・号・頁	48(1),pp.46-65
著者・共著者	Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, and Akira Matsuzawa
概要	This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196and 427 mW for 16QAM in transmitting and receiving modes, respectively. Inthe analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in theorganic package can transmit 3.1 Gb/sover 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM. 副筆